This invention is generally related to processor and instruction set architectures, and more particularly to processors for which certain higher level instructions may be translated into lower level instructions, prior to execution.
Certain processors have an internal hardware architecture that is designed to execute lower level instructions that typically have a fixed length and limited functionality, as compared to higher level instructions. For instance, the x86(trademark) instruction set by Intel Corp. is an example of a higher level instruction set that has variable length instructions as well as instructions which require several different operations to be performed by the processor. In contrast, reduced instruction set computing (RISC) instructions are deemed to be lower level instructions because they may be of fixed length and support relatively few operations per instruction. Processors that have internal execution hardware that is designed for lower level instructions are equipped with decoders for translating higher level instructions into the lower level instructions prior to execution. A higher level instruction may be translated into one or more lower level instructions.
One of the problems encountered in the translation is how to optimize the fixed length of a lower level instruction set in view of the variable-length permitted with higher level instructions. Sometimes a higher level instruction set allows variable size immediates (constants). In that case, the length of the lower level instruction set may be at least as large as needed to accommodate the largest immediate defined in the higher level instruction set. However, when a program uses mostly smaller-size immediates, the resulting translated lower level instructions consume a large amount of storage area in the processor (for instance, in the processor""s translated instruction cache) despite the fact that the program contains mostly smaller-sized immediates, so that much of the storage area in the cache is in effect being wasted.